In high speed synchronous integrated circuits such as memory interfaces, delay locked loops (DLLs) are used to align the clock edge and eliminate the clock skew. In double data rate (“DDR”) systems, DLLs are used to delay strobes by a fraction of a cycle delay, for example 90 degrees for a quarter cycle delay. A traditional way to perform this is to use a master DLL to lock a master delay line to one cycle delay. For the example of 90 degrees, the master delay line is used to configure a slave delay line to a quarter cycle delay by enabling ¼ of the delay cells, so the master delay line uses four times the area and power of the slave delay line. There is a need to be more efficient in terms of area and power for a DLL.